1. Field of the Invention
The invention relates to a method for testing a dynamic memory circuit, and to a test circuit for carrying out the method.
2. Description of the Related Art
After the fabrication of integrated dynamic memory circuits, the memory circuits have to be tested for their specification-conforming functioning, in order to identify defects. Identified defects can then generally be repaired by replacing the memory areas in which a defect has occurred by memory areas provided in redundant fashion.
A defect is identified by firstly writing test data to the memory circuit and subsequently reading out the test data. By comparing the test data written in and the data read out, a defect is identified if the test data and the data read out differ.
Data are read from an integrated memory circuit with the aid of sense amplifiers. Depending on the position in the memory circuit, the sense amplifiers are connected to one or two bit line pairs. Each of the bit line pairs may be connected to the sense amplifier via a separate switching device. Furthermore, word lines are provided. Memory cells are situated at the crossover points between the word lines and a respective one of the bit lines of the respective bit line pair. The memory cells have a memory transistor and a storage capacitance, which is applied to the corresponding bit line under the control of the corresponding word line connected to the control input of the memory transistor. The charge difference thereby effected on the bit lines of the corresponding bit line pair is conducted via the corresponding switching device to the sense amplifier and amplified there.
The components of the integrated memory circuit are subject to fluctuations in a process-dictated manner, so that the parameters thereof change. Thus, by way of example, the capacitance of the storage capacitance may fluctuate from memory cell to memory cell and thus effect different charge differences on the bit lines of the bit line pair. For proper functioning, even small charge differences effected by memory cells with a small storage capacitance have to be amplified correctly by the sense amplifier.
It is also possible that the sense amplifier and the switching device by which the sense amplifier and the bit line pairs can be connected to one another are subject to process-dictated fluctuations. By way of example, they may switch the switching devices more slowly or more rapidly than prescribed by the specification, or the two bit lines of the relevant bit line pair are connected to or isolated from the sense amplifier in a different way, i.e., at different speeds. Moreover, by virtue of process-dictated weak or incorrectly dimensioned transistors, the sense amplifier may be too slow to carry out a sufficiently rapid and sufficiently large amplification of the charge difference on the bit lines in all cases.